ITC 2007 - Call for Participation

CALL FOR PARTICIPATION

ITC 2007 -- ATE: Vision 2020 -- DBT 2007 -- DfM&Y 2007 -- TTEP Tutorials -- Registration

ITC 2007

International Test Conference 2007
"Facing Nanometer-technology Test Challenges"
Santa Clara, CA, USA
October 23 - 25, 2007

International Test Conference 2007 will again be held in Santa Clara from October 23–25 2007. The TestWeek™ 2007 Advance Program is now available http://www.itctestweek.org/; see the At-a-Glance schedule for a summary. Register, and make your hotel reservations online.

International Test Conference, the cornerstone of TestWeek™, is the world's premier conference dedicated to the electronic test of devices, boards and systems-covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals can confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers. 16 state-of-the-art full day tutorials on key test topics are also offered.

With the theme "Facing Nanometer-Technology Test Challenges," the 2007 conference will focus on breakthrough ideas to address the challenges of providing high-quality, cost-effective tests for nanometer-technology designs.

ATE: Vision 2020

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The workshop will examine where the ATE industry is heading in the near-term as well as in the long-term. Integrated circuits get denser, larger, and faster and more heterogeneous. As the number of dies in a single package increases, so does the test quality target. Certain dies require Known-Good-Die (KGD) quality levels, whereas more complex failure modes already challenge our yield learning curves.

These issues, when added to increasing Cost-Of-Test (COT), Time-To-Volume (TTV), and Time-To-Market (TTM) pressures, driven by today’s high-volume market applications, pose significant challenges to the ATE industry. To meet those challenges the industry needs to innovate in areas such as test methodologies, interconnection technologies, architectures, and Design-For-Testability (DFT) and Design-For-Manufacturability (DFM) technologies.

The goal of this workshop is to create an informal forum to discuss those innovations relevant to ATE developers and users. We are looking for solutions to the issues of 2010 and beyond, not those of 2008. Are our roadmaps addressing future test challenges? Are we investing our research dollars in the right areas? Do we have the right business models in place to succeed in the future? Join the discussion!

Representative topics include, but are not limited to:

Design for Testability (BIST, BISR)
Test methods for future defects
Adaptive Design Techniques
ATE/EDA Link
High-speed IO ATE
Low-cost ATE
RF ATE
ATE for Statistical Test

General Chair: Erik Volkerink, erik.volkerink@verigy.com
Program Chair: Scott Davidson, Scott.Davidson@sun.com

For more information, visit the web at: http://www.ATEVision.com

DBT 2007

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THEME: Process Variations + Systematic Defects: Can DBT Help?

As we push deeper into nanometer technologies, systematic defects are outstretching random defects as the dominant yield limiter and are presenting unique challenges to the yield enhancement community. New methodologies are required to detect, monitor, and resolve systematic defect mechanisms at the 90nm technology node and below. As mainstream silicon manufacturing processes scale to and beyond the 65-nm node, we also find the mean and variance of process variations increasing. Fallout caused by systematic defects is obfuscated by process variations, making them more difficult to distinguish using traditional testing methods. This year's workshop is charged with determining whether defect-based test is better positioned to provide information regarding root cause, and whether such methods can help with the identification and isolation of systematic defects.

The IEEE International Workshop on Current and Defect Based Testing (DBT 2007) is aimed at addressing these issues and others related to this year’s theme “Process Variations + Systematic Defects: Can DBT Help?” Paper presentations on topics related to the workshop’s theme and to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

The workshop includes (but is not limited to) the following topics:

Test Data Analysis
Transition and Delay Testing
IDDQ and IDDT Testing
Low voltage Testing
Noise and Cross-talk Testing
Defect Coverage & Metrics
Economics of Defect Based Testing
Outlier Identification
Data-Mining approaches for Test Data Processing
Elevated Voltage Testing and Stress Testing
Reliability and Yield
Nanometer Test Challenges
Mixed Current/Voltage Testing
Fault Localization & Diagnosis
Data-Based Testing

General Chair: Hans Manhaeve, Hans.Manhaeve@qstar.be
Program Chair: Mohammad Tehranipoor, tehrani@engr.uconn.edu

For more information, visit the web at: http://dbt.tttc-events.org/

DfM&Y 2007

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Increased manufacturing variability in leading-edge process technologies requires new paradigms and solution technologies for yield optimization. SoC manufacturability and yield entails design-specific optimization of the manufacturing, and thus enhanced communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools have been proposed in recent years. Some of these tools are leveraged during back-end design, others are applied post-GDSII (just before manufacturing handoff), and still others are applied post-design, from reticle enhancement and lithography through wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment, and choosing the most cost effective one(s) requires careful analysis of integration and schedule overheads, versus quantified benefits. This workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today’s SoC designs.

Representative topics include, but are not limited to:

Electrical, Design-Driven DFM
Built-in Repair Analysis and Self-Repair
Random Defectivity and Critical Area
Adaptive Design Techniques in DFM/DFY
Embedded Test and Diagnosis
Infrastructure IP
OPC and RET
Analog and mixed-signal DFM
Process Monitoring IP
Statistical Design
Test-based Yield Learning
Variability-aware Design
Yield Enhancement IP
Yield Management

General Chair: Yervant Zorian, zorian@viragelogic.com
Program Chair: Andrew B. Kahng, abk@cs.ucsd.edu

For more information, visit the web at: http://vlsicad.ucsd.edu/DFMY2007/

TTEP Tutorials

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The Tutorials & Education Group of the IEEE Computer Society Test Technology Technical Council (TTTC) presents a comprehensive set of sixteen full-day tutorials on topics of current interest to test professionals and researchers at ITC Test Week 2007 in Santa Clara, California. All tutorials qualify for credit towards IEEE TTTC certification under the TTEP program. Eight tutorials will be held on Sunday, October 21st, and eight on Monday, October 22nd. The titles of tutorials are listed below.

For more details and registration information on the 2007 ITC/TTEP tutorials see the ITC Test Week 2007 Advance Program and Registration on www.itctestweek.org.

Admission for on-site registrants is subject to availability.

Tutorials 1-8: Sunday, Oct. 21, 8:30 a.m. - 4:30 p.m.
Tutorial 1: DFX: The Convergence of Yield, Manufacturing, and Test – R. Aitken
Tutorial 2: Delay Testing: Theory and Practice – N. Tendolkar, S. Patil
Tutorial 3: Statistical Screening Methods Targeting “Zero Defect” IC Quality and Reliability – A. Singh
Tutorial 4: Dealing With Timing Issues for Sub-100n Designs - From Modeling to Mass Production – Li-C Wang, M.Abadir
Tutorial 5: Practices in Analog, Mixed-Signal and RF Testing – S. Abdennadher, S. Shaikh
Tutorial 6: Test Strategies for System-In-Package – Y. Zorian
Tutorial 7: Memory Test Challenges - A Practical and Implementation View Of BIST And Other DFT Techniques – V. Jayaram, S. Lai
Tutorial 8: Digital Timing Measurements - From Scopes and Probes To Timing And Jitter – W. Maichen

Tutorials 9-16: Monday, Oct. 22, 8:30 a.m. - 4:30 p.m.
Tutorial 9: IEEE 1500 - Building a Compliant Wrapper – T. Mclaurin, F. Da Silva, T. Waayers
Tutorial 10: Delay Test: A Practical Approach – A. Cron, B. Kruseman
Tutorial 11: Advanced Memory Testing – Ad Van De Goor
Tutorial 12: Scan Compression Techniques: Theory and Practice – R. Parekhji, T. Williams, R. Kapur,
J. Abraham
Tutorial 13: Wafer Probe Test Technology – W. Mann, J. Broz
Tutorial 14: Design for Manufacturability – Y. Zorian, J.-A.Carballo
Tutorial 15: Understanding Failure Mechanisms and Test Methods in Nanometer Technologies – J.Segura, C.Hawkins
Tutorial 16: Design for Testability for RF Circuits and Systems – M.Margala, S.Ozev

For more information on TTEP annual tutorials program, please visit: http://tab.computer.org/tttc/teg/ttep/

Registration

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For more information on registration please visit the online registration.

For more information, visit the web at: http://www.itctestweek.org/

The International Test Conference (ITC'07) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).